Semiconductor memories can be classified as volatile (where stored information is lost upon power removal) and non-volatile (where stored information is maintained after power removal, and which can be accurately retrieved upon subsequent power-up). Several types of non-volatile semi-conductor memories are known, notably based on MNOS transistors, FAMOS transistors, or FATMOS transistors. A description of prior MNOS and FAMOS memory circuits is given in U.S. Pat. No. 4,132,904. The latter patent, together with U.K. Specification No. 2,000,407 describe and claim FATMOS non-volatile latch memory circuits.
The FATMOS is basically a control gate plus floating gate MOS transistor with a portion of the floating gate lying close to the semiconductor substrate. When the source and drain connections are connected to an appropriate potential (one positive relative to the other) and a suitable potential of a first magnitude applied to the control gate, the transistor conducts. Upon removal of the control gate potential, conduction ceases. If a potential of a second and higher magnitude is applied to the control gate with the drain at zero voltage, the transistor again conducts, but in addition electric charges tunnel between the floating gate and the transistor substrate through the portion of the floating gate closest to the substrate. This charge remains on the floating gate even when the control gate potential is removed and increases the switching threshold of the device. This charge on the floating gate enables the transistor to be employed in a non-volatile memory, as described in U.K. Specification No. 2,000,407. The switching threshold of the FATMOS is returned to its original level by applying between the control gate and drain a potential of approximately the second and higher potential, but of opposite sign.
In a typical example of an N-channel enhancement-type FATMOS, the area of the floating gate closest to the substrate overlies the drain of the transistor, although this is not essential and the area closest to the substrate can be elsewhere on the transistor. In normal, non-volatile operation of a latch including such a FATMOS device, a voltage of typically +5 to +7 volts is applied to the control gate of the FATMOS. To write non-volatile information into the latch, a voltage of typically +8 to +15 volts is applied to the control gate of the FATMOS. If power is removed from the latch and then subsequently restored, it settles into a logic state dictated by its state during the earlier non-volatile write operation. In fact, the logic state it settles into is opposite to the state which existed at non-volatile write.
Although FATMOS transistors work well when employed in non-volatile memory cells (see U.K. Specification No. 2,000,407) they can sometimes be unpredictable during power-up after the FATMOS's have been placed in their non-volatile mode (higher threshold state). This unpredictablity manifests itself by the FATMOS transistor(s) switching to the wrong state (i.e. a FATMOS with a charge retained on its floating gate being held "off" instead of "on" and vice-versa). The explanation for this appears to arise from the processing conditions employed to produce the N.sup.+ diffusion areas. These have a higher capacitance per unit area than other semiconductor areas, and the consequence is that the device has more nodal capacity to the negative supply line than the positive line. If, for example, one examines the CMOS non-volatile memory cell illustrated in FIG. 2a of U.S. Pat. No. 4,132,904 (which employs a pair of FATMOS drivers in a cross-coupled latch configuration), the capacitance which exists between N1 and N2 to the more negative supply rail (V.sub.SS) is greater than the corresponding capacitance to the more positive supply rail V.sub.DD. Thus, when the cell is switched on after the FATMOS transistors (Q.sub.2 and Q.sub.4) have been placed in their varied threshold states, the P-channel complementary driver or load transistors (Q.sub.1 and Q.sub.3) switch on faster than the FATMOS devices. They will thus make a decision regarding conduction states ahead of the FATMOS devices. The latter transistors may therefore possibly be driven into the incorrect states and are thus incapable of steering the latch into its correct, non-volatile memory state.
The present invention is concerned with reducing this unpredictability during non-volatile read and is also concerned with enabling the non-volatile information written into the memory to be recovered without the need for the cycle of removing and then restoring the power to the latch.